High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Table 3.3 LAN Port 1 & 2 Power and Common Pins (continued)
BUFFER
TYPE
PIN
NAME
SYMBOL
DESCRIPTION
+3.3V Port 2
AnalogPower
Supply
VDD33A2
P
P
P
+3.3V Port 2 Analog Power Supply
122,125
Refer to the LAN9312 application note for
additional connection information.
+3.3V Master
Bias Power
Supply
VDD33BIAS
VDD18TX2
+3.3V Master Bias Power Supply
120
121
Refer to the LAN9312 application note for
additional connection information.
Port 2
Transmitter
+1.8V Power
Supply
Port 2 Transmitter +1.8V Power Supply: This pin
is supplied from the internal PHY voltage regulator.
This pin must be tied to the VDD18TX1 pin for
proper operation.
Refer to the LAN9312 application note for
additional connection information.
Port 1
Transmitter
+1.8V Power
Supply
VDD18TX1
P
+1.8V Port 1 Transmitter Power Supply: This pin
must be connected directly to the VDD18TX2 pin
for proper operation.
118
Refer to the LAN9312 application note for
additional connection information.
Table 3.4 Host Bus Interface Pins
BUFFER
PIN
NAME
SYMBOL
TYPE
DESCRIPTION
4-6,
8-12,
Host Bus
Data
D[31:0]
IS/O8
Host Bus Data High: Bits 31-0 of the Host Bus 32-
bit data port.
15-17,19,
20,22-26,
28-32,
Note:
Big and little endianess is supported.
34-38,
41-44
Host Bus
Address
A[9:2]
IS
Host Bus Address: 9-bit Host Bus Address Port
used to select Internal CSR’s and TX and RX
FIFO’s.
45,47,
49-53,
55
Note:
The A0 and A1 bits are not used because
the LAN9312 must be accessed on
DWORD boundaries.
Read Strobe
Write Strobe
Chip Select
nRD
nWR
nCS
IS
IS
IS
Read Strobe: Active low strobe to indicate a read
cycle. This signal is qualified by the nCS chip
select.
57
Write Strobe: Active low strobe to indicate a write
cycle. This signal is qualified by the nCS chip
select.
58
59
Chip Select: Active low signal used to qualify read
and write operations.
Revision 1.2 (04-08-08)
SMSC LAN9312
DATA3S0HEET
SMSC [ SMSC CORPORATION ]
