High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Note 3.1 The pin names for the twisted pair pins apply to a normal connection. If HP Auto-MDIX is
enabled and a reverse connection is detected or manually selected, the RX and TX pins
will be swapped internally.
Table 3.2 LAN Port 2 Pins
BUFFER
TYPE
PIN
NAME
SYMBOL
DESCRIPTION
Port 2 LED
Indicators
nP2LED[3:0]
OD12
LED indicators: When configured as LED outputs
via the LED Configuration Register (LED_CFG),
these pins are open-drain, active low outputs and
the pull-ups and input buffers are disabled. The
functionality of each pin is determined via the
LED_CFG[9:8] bits.
General
Purpose I/O
Data
GPIO[7:4]
IS/O12/
OD12
(PU)
General Purpose I/O Data: When configured as
GPIO via the LED Configuration Register
(LED_CFG), these general purpose signals are
fully programmable as either push-pull outputs,
open-drain outputs or Schmitt-triggered inputs by
writing the General Purpose I/O Configuration
Register (GPIO_CFG) and General Purpose I/O
Data & Direction Register (GPIO_DATA_DIR). The
pull-ups are enabled in GPIO mode. The input
buffers are disabled when set as an output.
83-86
Note:
See Chapter 13, "GPIO/LED Controller,"
on page 162 for additional details.
Port 2
Ethernet TX
Negative
TXN2
TXP2
RXN2
RXP2
AIO
AIO
AIO
AIO
Ethernet TX Negative: Negative output of Port 2
Ethernet transmitter. See Note 3.2 for additional
information.
127
126
124
123
Port 2
Ethernet TX
Positive
Ethernet TX Positive: Positive output of Port 2
Ethernet transmitter. See Note 3.2 for additional
information.
Port 2
Ethernet RX
Negative
Ethernet RX Negative: Negative input of Port 2
Ethernet receiver. See Note 3.2 for additional
information.
Port 2
Ethernet RX
Positive
Ethernet RX Positive: Positive input of Port 2
Ethernet receiver. See Note 3.2 for additional
information.
Note 3.2 The pin names for the twisted pair pins apply to a normal connection. If HP Auto-MDIX is
enabled and a reverse connection is detected or manually selected, the RX and TX pins
will be swapped internally.
Table 3.3 LAN Port 1 & 2 Power and Common Pins
BUFFER
PIN
NAME
SYMBOL
TYPE
DESCRIPTION
Bias
Reference
EXRES
AI
Bias Reference: Used for internal bias circuits.
Connect to an external 12.4K ohm, 1% resistor to
ground.
119
+3.3V Port 1
AnalogPower
Supply
VDD33A1
P
+3.3V Port 1 Analog Power Supply
114,117
Refer to the LAN9312 application note for
additional connection information.
SMSC LAN9312
Revision 1.2 (04-08-08)
DATA2S9HEET
SMSC [ SMSC CORPORATION ]
