High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
BITS
8:7
6
DESCRIPTION
TYPE
DEFAULT
RESERVED
RO
-
PME Buffer Type (PME_TYPE)
When this bit is cleared, the PME pin functions as an open-drain buffer for
use in a wired-or configuration. When set, the PME pin is a push-pull driver.
R/W
NASR
0b
Note:
When PME is configured as an open-drain output, the PME_POL
field of this register is ignored and the output is always active low.
0: PME pin open-drain output
1: PME pin push-pull driver
5
Wake On LAN Status (WOL_STS)
This bit indicates that a wake-up frame or magic packet was detected by the
Host MAC.
R/WC
0b
In order to clear this bit, it is required that the event in the Host MAC be
cleared as well. The event sources are described in Section 4.3, "Power
Management," on page 46.
4
3
RESERVED
RO
-
PME Indication (PME_IND)
R/W
0b
The PME signal can be configured as a pulsed output or a static signal,
which is asserted upon detection of a wake-up event. When set, the PME
signal will pulse active for 50mS upon detection of a wake-up event. When
cleared, the PME signal is driven continuously upon detection of a wake-up
event.
0: PME 50mS pulse on detection of event
1: PME driven continuously on detection of event
The PME signal can be deactivated by clearing the WOL_STS bit or by
clearing the appropriate enable.
2
1
0
PME Polarity (PME_POL)
R/W
NASR
0b
0b
0b
This bit controls the polarity of the PME signal. When set, the PME output
is an active high signal. When cleared, it is active low.
Note:
When PME is configured as an open-drain output, this field is
ignored and the output is always active low.
0: PME active low
1: PME active high
PME Enable (PME_EN)
When set, this bit enables the external PME signal pin. When cleared, the
external PME signal is disabled.
R/W
Note:
This bit does not affect the PME_INT interrupt bit of the Interrupt
Status Register (INT_STS).
0: PME pin disabled
1: PME pin enabled
Device Ready (READY)
RO
When set, this bit indicates that the LAN9312 is ready to be accessed. Upon
power-up, nRST reset, soft reset, or digital reset, the host processor may
interrogate this field as an indication that the LAN9312 has stabilized and is
fully active.
This bit can cause an interrupt if enabled.
Note:
With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and
RESET_CTL registers, read access to any internal resources is
forbidden while the READY bit is cleared. Writes to any address
are invalid until this bit is set.
Note:
This bit is identical to bit 27 of the Hardware Configuration Register
(HW_CFG).
SMSC LAN9312
265
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
