High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
BITS
DESCRIPTION
Transmit Threshold Mode (TTM)
TYPE
DEFAULT
21
R/W
0b
This bit is used to control the transmit threshold the Host MAC uses as
shown in the two tables in the TR field of this register. This bit is ignored
when the SF bit is set.
This bit should be set to '1' when operating in 10Mbps mode, and cleared
to '0' when operating in 100Mbps mode.
20
Store and Forward (SF)
When set, this bit instructs the Host MAC to store a frame of transmit data
before starting transmission.
R/W
0b
If this bit is set, the TTM and TR bits (21,13, and 12) are not used.
If this bit is reset, the transmission is started before the entire frame is input
from the HBI (Host Bus Interface). TTM and TR (see bit 21,13, and 12)
determine when the Host MAC initiates the transmission. If the host cannot
keep up, there is a risk of an Underrun Error.
19:16
TX FIFO Size (TX_FIF_SZ)
R/W
5h
This field sets the size of the TX FIFOs in 1KB values to a maximum of
14KB. The TX Status FIFO consumes 512 bytes of the space allocated by
TX_FIF_SIZ, and the TX Data FIFO consumes the remaining space
specified by TX_FIF_SZ. The minimum size of the TX FIFOs is 2KB (TX
Data FIFO and Status FIFO combined). The TX Data FIFO is used for both
TX data and TX commands.
The RX Status and Data FIFOs consume the remaining space, which is
equal to 16KB minus TX_FIF_SIZ. See section Section 9.7.3, "FIFO
Memory Allocation Configuration," on page 121 for more information.
15:14
13:12
RESERVED
RO
-
Threshold Control Bits (TR)
R/W
00b
This field controls the transmit threshold values the Host MAC should use.
These bits are used when the SF bit is reset. The host can program the
Transmit threshold by setting these bits. The intent is to allow the Host MAC
to start transferring data only after the threshold value is met.
In 10Mbps mode (TTM = 1) the threshold is set as follows:
[13]
0
[12]
0
Threshold (DWORD’s)
012h
018h
020h
028h
0
1
1
0
1
1
In 100Mbps mode (TTM = 0) the threshold is set by as follows:
[13]
0
[12]
0
Threshold (DWORD’s)
020h
040h
080h
100h
0
1
1
0
1
1
Revision 1.2 (04-08-08)
262
SMSC LAN9312
DATASHEET