High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.2.9.7
Free Running 25MHz Counter Register (FREE_RUN)
Offset:
09Ch
Size:
32 bits
This read-only register reflects the current value of the free-running 25MHz counter. Refer to Section
12.2, "Free-Running Clock," on page 161 for additional information.
BITS
DESCRIPTION
Free Running Counter (FR_CNT)
TYPE
DEFAULT
31:0
RO
00000000h
This field reflects the current value of the free-running 32-bit counter. At
reset, the counter starts at zero and is incremented by one every 25MHz
cycle. When the maximum count has been reached, the counter will rollover
to zero and continue counting.
Note:
The free running counter can take up to 160nS to clear after a reset
event.
Revision 1.2 (04-08-08)
268
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
