High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.2.9.2
Byte Order Test Register (BYTE_TEST)
Offset:
064h
Size:
32 bits
This read-only register can be used to determine the byte ordering of the current configuration. Byte
ordering is a function of the host data bus width and endianess. Refer to Section 8.3, "Host Endianess,"
on page 99 for additional information on byte ordering.
Note: This register can be read while the LAN9312 is in the reset or not ready states.
The BYTE_TEST register can optionally be used as a dummy read register when assuring minimum
write-to-read or read-to-read timing. Refer to Section 8.4.2, "Special Restrictions on Back-to Back
Write-Read Cycles," on page 101 and Section 8.4.3, "Special Restrictions on Back-to-Back Read
Cycles," on page 105 for additional information.
BITS
DESCRIPTION
TYPE
DEFAULT
87654321h
31:0
Byte Test (BYTE_TEST)
This field reflects the current byte ordering
RO
Revision 1.2 (04-08-08)
260
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
