High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.2.8.8
Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)
Offset:
1DCh
Size:
32 bits
Index (decimal): 31
This read/write register contains a current link speed/duplex indicator and SQE control.
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
RESERVED
(See Note 14.42)
RO
-
15
14
RESERVED
RO
-
Switch Looopback MII
When set, transmissions from the switch fabric Port 0(Host MAC) are not
sent to the Host MAC. Instead, they are looped back into the switch engine.
R/W
0b
From the MAC viewpoint, this is effectively a FAR LOOPBACK.
If loopback is enabled during half-duplex operation, then the Enable Receive
Own Transmit bit in the Port x MAC Receive Configuration Register
(MAC_RX_CFG_x) must be set for this port. Otherwise, the switch fabric will
ignore receive activity when transmitting in half-duplex mode.
This mode works even if the Isolate bit of the Virtual PHY Basic Control
Register (VPHY_BASIC_CTRL) is set.
13:8
7
RESERVED
RO
-
Switch Collision Test MII
When set, the collision signal to the switch fabric Port 0(Host MAC) is active
during transmission from the switch engine.
R/W
0b
It is recommended that this bit be used only when using loopback mode.
6:5
4:2
RESERVED
RO
RO
-
Current Speed/Duplex Indication
This field indicates the current speed and duplex of the Virtual PHY link.
Note 14.43
[4]
0
[3]
0
[2]
0
Speed
Duplex
RESERVED
0
0
1
10Mbps
half-duplex
half-duplex
0
1
0
100Mbps
0
1
1
RESERVED
RESERVED
1
0
0
1
0
1
10Mbps
full-duplex
full-duplex
1
1
0
100Mbps
1
1
1
RESERVED
1
0
RESERVED
SQEOFF
RO
-
R/W
NASR
Note 14.44
Note 14.45
This bit enables/disables the Signal Quality Error (Heartbeat) test.
0: SQE test enabled
1: SQE test disabled
SMSC LAN9312
257
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
