FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
LAN91C110 REV. B REVISIONS
DATE
PAGE(S) SECTION/FIGURE/ENTRY
CORRECTION
Replaced block diagram.
REVISED
12
18
5
Figure 4 - LAN91C110 INTERNAL BLOCK
09-04-02
08-21-02
08-08-02
08-08-02
08-08-02
08-08-02
DIAGRAM WITH DATAPATH
Bank 0 Offset 2 – EPH Status Register
Changed the the RX OVRN bit to a
Reserved bit.
Table 1 - DESCRIPTION OF PIN
FUNCTIONS
Renamed pin nARDY to active high ARDY
12
17
29
Figure 4 - LAN91C110 INTERNAL BLOCK
DIAGRAM WITH DATAPATH
Modified the block diagram
Bank 0 Offset 0—Transmit Control Register Modified the description of the FDUPLX bit
and the PAD_EN bit
Bank 2 Offset C—Interrupt Status Register
Modified the description of the Interrupt
Register bits
31
36
49
Figure 6 - INTERRUPT STRUCTURE
Typical Flow of Events for Transmit
Modified the interrupt structure figure
Modified the Transmit Flow Routine
08-08-02
08-08-02
08-08-02
Timing diagrams and SRAM Application
Note
Add new parameters to the SRAM
Interface timing diagram and modified the
application node
SMSC DS – LAN91C110 REV. B
Page 55
Rev. 09/05/02
SMSC [ SMSC CORPORATION ]
