FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
TIMING DIAGRAMS
ADDRESS
nADS
A1-A15, AEN, nBE0-nBE1 valid
t3
t4
READ DATA
nRD, nWR
t2
t1
t5A
t5
WRITE DATA
D0-D15 valid
FIGURE 13 - ASYNCHRONOUS CYCLE - NADS=0
PARAMETER
MIN
TYP
MAX
UNITS
t1
t2
A1-A15, AEN, nBE0-nBE1 Valid and nADS Low Setup to
nRD, nWR Active
25
ns
A1-A15, AEN, nBE0-nBE1 Hold After nRD, nWR Inactive
(Assuming nADS Tied Low)
20
ns
t3
t4
nRD Low to Valid Data
40
30
ns
ns
ns
ns
nRD High to Data Floating
t5
Data Setup to nWR Inactive
30
5
t5A
Data Hold After nWR Inactive
ADDRESS
valid
t9
A1-A15, AEN, nBE0-nBE1
t8
nADS
t3
t4
READ DATA
nRD, nWR
t1
t5A
t5
D0-D15 valid
WRITE DATA
FIGURE 14 - ASYNCHRONOUS CYCLE - USING NADS
PARAMETER
MIN TYP MAX UNITS
t1
A1-A15, AEN, nBE0-nBE1 Valid and nADS Low Setup to nRD,
nWR Active
25
ns
t3
t4
t5
nRD Low to Valid Data
40
30
ns
ns
ns
ns
ns
ns
nRD High to Data Floating
Data Setup to nWR Inactive
30
5
t5A
t8
Data Hold After nWR Inactive
A1-A15, AEN, nBE0-nBE1 Setup to nADS Rising
A1-A15, AEN, nBE0-nBE1 Hold after nADS Rising
10
15
t9
SMSC DS – LAN91C110 REV. B
Page 49
Rev. 09/05/02
SMSC [ SMSC CORPORATION ]
