FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
t50
t54
t50
t34
t35
t38
t51
RA2-RA16
t39
t36
t37
nRWE0-nRWE3
t52
t53
nROE
RD0-RD31
WRITE CYCLE
READ CYCLE
t50
t39
t50
t54
t38
t51
t34
t35
RA2-RA16
t36
t37
nRWE0-nRWE3
t52
t53
nROE
RD0-RD31
READ CYCLE
WRITE CYCLE
t50
t51
t38
t51
t38
t51
t38
t38
RA2-RA16
nRWE0-nRWE3
t52
nROE
RD0-RD31
MULTIPLE READ CYCLES
FIGURE 16 - SRAM INTERFACE
PARAMETER
MIN
0
TYP
MAX
UNITS
ns
t34
t35
t36
t37
t39
t54
t38
t51
t52
t53
t50
Write – RA2-RA16 Setup to nRWE0-nRWE3 Falling
Write – RA2-RA16 Hold after nRWE0-nRWE3 Rising
Write – RD0-RD31 Setup to nRWE0-nRWE3 Rising
Write – RD0-RD31 Hold after nRWE0-nRWE3 Rising
Write – nRWE0-nRWE3 Pulse Width
0
ns
12
0
15
12
ns
ns
ns
Write – RA2-RA16 Valid to End of Write
ns
Read – RA2-RA16 Valid to RD0-RD31 Valid
Read – RD0-RD31 Hold after RA2-RA16 Change
Read – nROE enable to RD0-RD31 Valid
Read – nROE disable to RD0-RD31 Invalid
Read/Write – Cycle Time
15
ns
3
ns
12
8
ns
0
25
ns
ns
SMSC DS – LAN91C110 REV. B
Page 51
Rev. 09/05/02
SMSC [ SMSC CORPORATION ]
