Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Start transmission process into the CSMA/CD block.
Generate CSMA/CD side addresses for accessing memory during transmit and receive operations.
Generate MMU memory requests and verify success.
Compute byte count and write it in first locations of receive packet.
Write transmit status word in first locations of transmit packet.
Determine if enough memory is available for reception.
De-allocate transmit memory after suitable completion.
De-allocate receive memory upon error conditions.
Initiate retransmissions upon collisions (if less than 16 retries).
Terminate reception and release memory if packet is too long.
The specific nature of each operation and its trigger event are:
1. TX operations will begin if TXENA is set and TX FIFO is not empty. The DMA logic does not need to
use the TX PACKET NUMBER, it goes directly from the FIFO to the MMU. However the DMA logic
controls the removal of the PACKET NUMBER from the FIFO.
2. Generation of CSMA/CD side addresses into memory: Independent 11-bit counters are kept for
transmit and receive in order to allow full-duplex operation.
3. MMU requests for allocation are generated by the DMA logic upon reception. The initial allocation
request is issued when the CSMA block indicates an active reception. If allocation succeeds, the DMA
block stores the packet number assigned to it, and generates write arbitration requests for as long as
the CSMA/CD FIFO is not empty. In parallel the CSMA/CD completes the address filtering and
notifies the DMA of an address match. If there is no address match, the DMA logic will release the
allocated memory and stop reception.
4. When the CSMA/CD block notifies the DMA logic that a receive packet was completed, if the CRC is
OK, the DMA will either write the previously stored packet number into the RX PACKET NUMBER
FIFO (to be processed by the CPU), or if the CRC is bad the DMA will just issue a release command
to the MMU (and the CPU will never see that packet).
Packets with bad CRC can be received if the RCV_BAD bit in the configuration register is set.
5. If AUTO_RELEASE is set, a release is issued by the DMA block to the MMU after a successful
transmission (TX_SUCC set), and the TX completion FIFO is clocked together with the TX FIFO
preventing the packet number from moving into the TX completion FIFO.
6. Based on the RX counter value, if a receive packet exceeds 1532 bytes, reception is stopped by the
DMA and the RX ABORT bit in the Receive Control Register is set. The memory allocated to the
packet is automatically released.
7. If an allocation fails, the CSMA/CD block will activate RX_OVRN INT upon detecting a FIFO full
condition. RXEN will stay active to allow reception of subsequent packets if memory becomes
available. The CSMA/CD block will flush the FIFO upon the new frame arrival.
9.7
Packet Number FIFOS
The transmit packet FIFO stores the packet numbers awaiting transmission, in the order they were
enqueued. The FIFO is advanced (written) when the CPU issues the "enqueue packet number
command", the packet number to be written is provided by the CPU via the Packet Number Register. The
number was previously obtained by requesting memory allocation from the MMU. The FIFO is read by the
DMA block when the CSMA/CD block is ready to proceed on to the next transmission. By reading the TX
EMPTY INT bit the CPU can determine if this FIFO is empty.
The transmit completion FIFO stores the packet numbers that were already transmitted but not yet
acknowledged by the CPU. The CPU can read the next packet number in this FIFO from the FIFO Ports
Register. The CPU can remove a packet number from this FIFO by issuing a TX INT acknowledge. The
CPU can determine if this FIFO is empty by reading the TX INT bit or the FIFO Ports Register.
Rev. 09/10/2004
Page 82
SMSC LAN91C965v&3v
DATASHEET
SMSC [ SMSC CORPORATION ]
