Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Chapter 9 Functional Description of the Blocks
9.1
Memory Management Unit
The MMU interfaces the on-chip RAM on one side and the arbiter on the other for address and data flow
purposes. For allocation and de-allocation, it interfaces the arbiter only.
The MMU deals with a single ported memory and is not aware of the fact that there are two entities
requesting allocation and actually accessing memory. The mapping function done by the MMU is only a
function of the packet number accessed and of the offset within that packet being accessed. It is not a
function of who is requesting the access or the direction of the access.
To accomplish that, memory accesses as well as MMU allocation and de-allocation requests are arbitrated
by the arbiter block before reaching the MMU.
Memory allocation could take some time, but the ALLOC INT bit in Interrupt Status Register is negated
immediately upon allocation request, allowing the system to poll that register at any time. Memory de-
allocation command completion indication is provided via the BUSY bit, readable through the MMU
command register.
The mapping and queuing functions of the MMU rely on the uniqueness of the packet number assigned to
the requester. For that purpose the packet number assignment is centralized at the MMU, and a number
will not be reused until the memory associated with it is released. It is clear that a packet number should
not be released while the number is in the TX or RX packet queue.
The TX and RCV FIFOs are deep enough to handle the total number of packets the MMU can allocate,
therefore there is no need for the programmer or the hardware to check FIFO full conditions.
9.2
Arbiter
The function of the arbiter is to sequence packet RAM accesses as well as MMU requests in such a way
that the on-chip single ported RAM and a single MMU can be shared by two parties. One party is the host
CPU and the other party is the CSMA/CD block.
The arbiter is address transparent, namely, any address can be accessed at any time. In order to exploit
the sequential nature of the access, and minimize the access time on the system side, the CPU cycle is
buffered by the Data Register rather than go directly to and from memory. Whenever a write cycle is
performed, the data is written into the Data Register and will be written into memory as a result of that
operation, allowing the CPU cycle to complete before the arbitration and memory cycle are complete.
Whenever a read cycle is performed, the data is provided immediately from the Data Register, without
having to arbitrate and complete a memory cycle. The present cycle results in an arbitration request for
the next data location. Loading the pointer causes a similar pre-fetch request.
This type of read-ahead and write-behind arbitration allows the controller to have a very fast access time,
and would work without wait states for as long as the cycle time specification is satisfied. The values are
40 ns access time, and 185ns cycle time.
By the same token, CSMA/CD cycles might be postponed. The worst case CSMA/CD latency for arbiter
service is one memory cycle. The arbiter uses the pointer register as the CPU provided address, and the
internal DMA address from the CSMA/CD side as the addresses to be provided to the MMU.
SMSC DS – LAN91C965v&3v
Page 79
Rev. 09/10/2004
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