Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
b) The previous empty condition is cleared (acknowledged)
TX INT - Set when at least one packet transmission was completed or any of the below transmit fatal
errors occurs:
1. TXUNRN - Transmit under-run
2. SQET - SQE Error
3. LOST CARR - Lost Carrier
4. LATCOL - Late Collision
5. 16COL - 16 collisions
The first packet number to be serviced can be read from the FIFO PORTS register. The TX INT bit is
always the logic complement of the TEMPTY bit in the FIFO PORTS register. After servicing a packet
number, its TX INT interrupt is removed by writing the Interrupt Acknowledge Register with the TX INT bit
set.
RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be read
from the FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the
FIFO PORTS register.
Receive Interrupt is cleared when RX FIFO is empty.
Notes:
For edge triggered systems, the Interrupt Service Routine should clear the Interrupt Mask Register, and only
enable the appropriate interrupts after the interrupt source is serviced (acknowledged).
Rev. 09/10/2004
Page 60
SMSC LAN91C965v&3v
DATASHEET
SMSC [ SMSC CORPORATION ]
