Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
I/O SPACE - BANK2
OFFSET
C
NAME
TYPE
READ ONLY
SYMBOL
IST
INTERRUPT STATUS REGISTER
RX_
TX
EMPTY
TX IDLE
INT
ERCV
INT
0
EPH
INT
0
OVRN
ALLOC
INT
INT
0
INT
1
TX INT
0
RCV INT
0
0
0
OFFSET
C
NAME
TYPE
SYMBOL
ACK
INTERRUPT ACKNOWLEDGE
WRITE ONLY
REGISTER
RX_
TX
EMPTY
ERCV
INT
OVRN
INT
INT
TX INT
OFFSET
D
NAME
TYPE
READ/WRITE
SYMBOL
MSK
INTERRUPT MASK REGISTER
RX_
TX
EMPTY
TX IDLE
INT
ERCV
EPH
INT
MASK
0
OVRN
ALLOC
INT
INT
MASK
0
INT
MASK
INT
TX INT
MASK
0
RCV INT
MASK
0
MASK
MASK
MASK
0
0
0
0
This register can be read and written as a word or as two individual bytes.
The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A
MASK bit being set will cause a hardware interrupt.
TX IDLE INT - Transmit Idle interrupt. Set when the transmit state machine is not active. This bit is used
under the condition where the TX FIFO is still NOT empty, the transmitter is disabled and the host wants to
determine when the transmitter is completed with the current transmit packet. This event usually happens
when the host wants to insert at the head of the transmit queue a frame for example.
Typical flow of events/Condition:
1. The transmit FIFO is not empty
2. The transmit DONE FIFO is either empty or not empty
3. The transmit engine is either active or not active
Flow of events for an insertion of a transmit packet:
1. Disable the Transmitter
2. Remove and release any “transmit done” packets in the TX FIFO
3. Via polling or an interrupt driven event, determine status of TX IDLE INT bit and wait until this bit is
set. This will determine when the transmitter is truly done with all transmit events.
4. Remove and store (if any, in software) Packet numbers from the transmit FIFO. (These packets will
later be restored into the TX FIFO after the control frame is inserted into the front of the TX FIFO).
5. Enable Transmitter
Rev. 09/10/2004
Page 58
SMSC LAN91C965v&3v
DATASHEET
SMSC [ SMSC CORPORATION ]
