Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
The I/O base decode defaults to 300h (namely, the high byte defaults to 18h). ROM SIZE defaults to 01.
ROM decode defaults to CC000 (namely the low byte defaults to 67h).
Below chart shows the decoding of I/O Base Address 300h:
A15 A14 A13 A12 A11 A10
A9
1
A8
1
A7
0
A6
0
A5
0
A4
0
A3
0
A2
0
A1
0
A0
0
0
0
0
0
0
0
I/O SPACE - BANK1
OFFSET
NAME
TYPE
READ/WRITE
SYMBOL
IAR
4 THROUGH 9
INDIVIDUAL ADDRESS REGISTERS
These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or
EEPROM reload. The registers can be modified by the software driver, but a STORE operation will not
modify the EEPROM Individual Address contents.
Bit 0 of Individual Address 0 register corresponds to the first bit of the address on the cable.
ADDRESS 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADDRESS 1
0
0
ADDRESS 2
0
0
ADDRESS 3
0
0
ADDRESS 4
0
0
ADDRESS 5
0
0
0
Rev. 09/10/2004
Page 50
SMSC LAN91C965v&3v
DATASHEET
SMSC [ SMSC CORPORATION ]
