Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
I/O SPACE - BANK1
OFFSET
A
NAME
TYPE
READ/WRITE
SYMBOL
GPR
GENERAL ADDRESS REGISTERS
HIGH DATA BYTE
0
0
0
0
0
0
0
0
0
LOW DATA BYTE
0
0
0
0
0
0
0
This register can be used as a way of storing and retrieving non-volatile information in the EEPROM to be
used by the software driver. The storage is word oriented, and the EEPROM word address to be read or
written is specified using the six lowest bits of the Pointer Register.
This register can also be used to sequentially program the Individual Address area of the EEPROM, that is
normally protected from accidental Store operations.
This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control
Register is set. This allows generic EEPROM read and write routines that do not affect the basic setup of
the LAN91C96.
I/O SPACE - BANK1
OFFSET
C
NAME
CONTROL REGISTER
TYPE
READ/WRITE
SYMBOL
CTR
0
RCV_
BAD
PWRDN
WAKEUP
_EN
AUTO
1
RELEAS
E
0
LE
ENABLE
0
CR
ENABLE
0
0
TE
ENABLE
0
0
0
X
X
1
EEPROM
SELECT
0
RELOAD
STORE
0
0
X
X
0
RCV_BAD - When set, bad CRC packets are received. When clear bad CRC packets do not generate
interrupts and their memory is released.
PWRDN - Active high bit used to put the Ethernet function in power down mode.
Cleared by:
1. A write to any register in the LAN91C96 I/O space.
2. Hardware reset. This bit is combined with the Pwrdwn bit in ECSR and with the powerdown bit to
determine when the function is powered down.
WAKUP_EN - Active high bit used to enable the controller in the appropriate power down modes to power
up and set the WAKEUP bit in the EPHSR -> generate an EPH interrupt(if not masked). When clear (0),
no “Magic Packet” scanning is done on receive packets.
Note:
Setting (1) the bit is meaningful only if the function is enabled (Enable Function bit in COR; offset 8000h)
SMSC LAN91C965v&3v
Page 51
Rev. 09/10/2004
DATASHEET
SMSC [ SMSC CORPORATION ]
