Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
t 1
t 2
t 2
CLOCK
t R
t F
Figure 12.26 – Input Clock Timing
NAME
t1
t2
DESCRIPTION
Clock Cycle Time for 20 MHz
Clock High Time/Low Time for 20 MHz
Clock Rise Time/Fall Time
MIN
TYP
50
MAX
UNITS
ns
ns
30/20
20/30
5
tR, tF
ns
Xtal1 Startup time (from 1.6v of Vcc rising)
50
20.3
msec
MHz
Xtal1 Capture Range (Xtal1 frequency
19.7
1
variation)
Xtal Internal feedback resistor
3
Meg Ohm
DATA
REGISTER
POINTER
REGISTER
ADDRESS
nIOWR
t45
Parameter
Last Access to Data Register to Pointer
min
2 * t20
typ
max
units
ns
t45
Reloaded
Figure 12.27 – Memory Write Timing
Rev. 09/10/2004
Page 122
SMSC LAN91C965v&3v
DATASHEET
SMSC [ SMSC CORPORATION ]
