Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
A0-15
VALID ADDRESS
AEN,
VALID ADDRESS
nSBHE
nIOCS16
t20
Z
nIORD
nIOWR
t9
Z
t10
IOCHRDY
Z
Z
Z
D0-D15
VALID DATA
VALID DATA
Parameter
min
typ
max
units
t9
t10
t20
Control Active to IOCHRDY Low
IOCHRDY Low Pulse Width*
Cycle time**
12
150
ns
ns
ns
100
185
*Note: Assuming NO WAIT ST = 0 in configuration register and cycle time observed.
**Note: The cycle time is defined only for accesses to the Data Register as follows:
For Data Register Read - From nIORD falling to next nIORD falling
For Data Register Write - From nIOWR rising to next nIOWR rising
Figure 12.6 – Local Bus Consecutive Read and Write Cycles
Rev. 09/10/2004
Page 104
SMSC LAN91C965v&3v
DATASHEET
SMSC [ SMSC CORPORATION ]
