Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
t51
t52
t50
A0-9,A15
nREG
valid
t47
t49
t55
t48
nCE1,nCE2
t20
t54
nIOWR
D0-15
valid
Parameter
min
typ
max
units
nREG Low Setup to Control Active
nCE1,nCE2 Setup to Control Active
nREG Hold after Control Inactive
nCE1,nCE2 Hold after Control Inactive
Address Setup to Control Active
Address Hold after Control Inactive
Cycle Time (No Wait States)
t47
t48
t49
t50
t51
t52
t20
t54
t55
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
15
25
15
185
30
9
Write Data Setup to nIOWR Rising
Write Data Hold after nIOWR Rising
Figure 12.5 - PCMCIA Consecutive Write Cycles
SMSC DS – LAN91C965v&3v
Page 103
Rev. 09/10/2004
DATASHEET
SMSC [ SMSC CORPORATION ]
