Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
t51
t52
A0-9,A15
nREG
valid
t49
t47
t48
t50
nCE1,nCE2
t20
nIORD
D0-15
t53
t46
valid
t46
nINPACK
Parameter
min
typ
max
units
t46
t47
t48
t20
t49
t50
t51
t52
t53
nIORD to INPACK Delay
0
5
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
nREG Low to Control Active
nCE1,nCE2 Setup to Control Active
Cycle Time (No Wait States)
nREG Hold after Control Active
nCE1,nCE2 Hold after Control Inactive
Address Setup to Control Active
Address Hold after Control Inactive
nIORD Active to Data Valid
5
185
0
15
25
15
0
40
Figure 12.3 - PCMCIA Consecutive Read Cycles
SMSC DS – LAN91C965v&3v
Page 101
Rev. 09/10/2004
DATASHEET