Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
t3
t10
t2
nAS(nAEN)
ADD
t4
t5
t6
xDS,LDS,UDS (nIORD)
R/nW(nIOWR)
t1
t7
t9
DATA
Figure 12.10 - 68000 Read Timing
MIN
0
TYP
MAX
UNIT
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
COMMENTS
R/nW asserted before nAS
nAS assertion time
Address setup time
Address hold time
nAS to xDS deassertion delay
xDS assertion time
Data setup time (Access time)
Data hold time
Consecutive reads cycle time
t1
t2
t3
t4
t5
t6
t7
t9
t10
45
15
10
0
45
10
0
30
75
Rev. 09/10/2004
Page 108
SMSC LAN91C965v&3v
DATASHEET