Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Chapter 12 Timing Diagrams
t63
t60
t62
t61
A0-9,A15
valid
t64
valid
t63
t60
nREG
nCE1
t57
nWE
nOE
t59
t65
t58
D0-7
valid
valid
Parameter
min
typ
max
units
t57
t58
t59
t60
t61
t62
t63
t64
t65
Write Data Setup to nWE Rising
Write Data Hold after nWE Rising
nOE Low to Valid Data
30
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
50
Address, nREG Setup to nWE Active
Address, nREG Hold after nOE Inactive
Address, nREG Setup to nOE Active
Address, nREG Hold after Control Inactive
nCE1 Setup to nWE Rising
25
15
25
15
60
0
nCE1 Low to Valid Data
Figure 12.1 – Card Configuration Registers – Read/Write PCMCIA Mode (A15=1)
SMSC DS – LAN91C965v&3v
Page 99
Rev. 09/10/2004
DATASHEET
SMSC [ SMSC CORPORATION ]
