Non-PCI Single-Chip Full Duplex Ethernet Controller
The data path routed by the arbiter goes between memory (the data path does not go through the MMU)
on one side and either the CPU side bus or the data path of the CSMA/CD core.
The data path between memory and the Data Register is in fact buffered by a small FIFO in each direction.
The FIFOs beneath the Data Register can be read and written as bytes or words, in any sequential
combination. The presence of these FIFOs makes sure that word transfers are possible on the system bus
even if the address loaded into the pointer is odd.
9.3
Bus Interface
The bus interface handles the data, address and control interfaces and is compliant with the Local Bus.
The functions in this block include address decoding for I/O and ROM memory (including address
relocation support) for Local Bus, data path routing, sequential memory address support, optional wait
state generation, boot ROM support, EEPROM setup function, bus transceiver control, and interrupt
generation / selection.
For Local Bus, I/O address decoding is done by comparing A15-A4 to the I/O BASE address determined in
part by the upper byte of the BASE ADDRESS REGISTER, and also requiring that AEN be low. If the
above address comparison is satisfied and the LAN91C96I is in 16 bit mode, nIOCS16 will be asserted
(low).
A valid comparison does not yet indicate a valid I/O cycle is in progress, as the addresses could be used
for a memory cycle, or could even glitch through a valid value. For Local Bus, only when nIORD or
nIOWR are activated the I/O cycle begins.
9.4
Wait State Policy
The LAN91C96I can work on most system buses without having to add wait states. The two parameters
that determine the memory access profile are the read access time and the cycle time into the Data
Register.
The read access time is 40ns and the cycle time is 185ns. If any one of them does not satisfy the
application requirements, wait states should be added.
If the access time is the problem, IOCHRDY should be negated for all accesses to the LAN91C96I. This
can be achieved by programming the NO WAIT ST bit in the configuration register to “0”. The LAN91C96I
will negate IOCHRDY for 100ns to 150ns on every access to any register.
If the cycle time is the problem, programming NO WAIT ST as described before will solve it but at the
expense of slowing down all accesses. The alternative is to let the LAN91C96I negate IOCHRDY only
when the Data Register FIFOs require so. Namely, if NO WAIT ST is set, IOCHRDY will only be negated if
a Data Register read cycle starts and there is less than a full word in the read FIFO, or if a write cycle
starts and there is more than two bytes in the write FIFO.
The cycle time is defined as the time between leading edges of read from the Data Register, or
equivalently between trailing edges of write to the Data Register. For example, in an Local Bus system
the cycle time of a 16 bit transfer will be at least 2 clocks for the I/O access to the LAN91C96I (+ one clock
for the memory cycle) for a total of 3 clocks. In absolute time it means 375ns for an 8MHz bus, and 240ns
for a 12.5 MHz bus.
The cycle time will not increase when configured for full duplex mode, because the CSMA/CD memory
arbitration requests are sequenced by the DMA logic and never overlap.
Rev. 11/18/2004
Page 74
SMSC DS – LAN91C96I
DATASHEET
SMSC [ SMSC CORPORATION ]
