Non-PCI Single-Chip Full Duplex Ethernet Controller
The FIFO is read out upon CPU command (remove packet from top of RX FIFO, or remove and release
command) after processing the receive packet in the receive area.
The width of each FIFO is 5 bits per packet number. The depth of each FIFO equals the number of
packets the LAN91C96I can handle (18).
The guideline is software transparency; the software driver should not be aware of different devices or
FIFO depths. If the MMU memory allocation succeeded, there will be room in the transmit FIFO for
enqueuing the packet. Conversely if there is free memory for receive, there should be room in the receive
FIFO for storing the packet number.
Note that the CPU can enqueue a transmit command with a packet number that does not follow the
sequence in which the MMU assigned packet numbers. For example, when a transmission failed and it is
retried in software, or when a receive packet is modified and sent back to the network.
Figure 9.1 - MMU Packet Number Flow and Relevant Registers
9.8
CSMA Block
The CSMA/CD block is first interfaced via its control registers in order to define its operational
configuration. From then on, the DMA interface between the CSMA/CD block and memory is used to
transfer data to and from its data path interface.
SMSC DS – LAN91C96I
Page 77
Rev. 11/18/2004
DATASHEET
SMSC [ SMSC CORPORATION ]
