Non-PCI Single-Chip Full Duplex Ethernet Controller
8.6
Power Down
The LAN91C96I can enter power down mode by means of the PWRDWN pin (pin 68) or the PWRDN bit
(Control Register, bit 13). When in power down mode, the LAN91C96I will:
Stop the crystal oscillator
Tristate:
Data Bus
Interrupts(only by PWRDN bit)
nIOCS16
10BASE-T and AUI outputs
Turn off analog bias currents
Drive the EEPROM and ROM outputs inactive
Preserve contents of registers and memory
The PWRDWN pin is internally gated with the RESET (RESET pin before de-glitching) and with the
SRESET bit (COR bit 7). This gating function internally negates power down whenever RESET is high or
SRESET is high to allow the oscillator to run during RESET. Except for this gating function, all other uses
of the RESET pin use a de-glitched version of the signal as defined in the pin description section.
NXENDEC PIN
PWRDN PIN
PWRDN BIT
0
1
1
X
0
1
0
0
0
Normal external ENDEC operation
Normal internal ENDEC operation
Powerdown - Normal mode restored by
PWRDWN pin going low
Powerdown - Bit is cleared by a write
access to any LAN91C96I register or by
hardware reset
X
X
1
SMSC DS – LAN91C96I
Page 71
Rev. 11/18/2004
DATASHEET
SMSC [ SMSC CORPORATION ]
