Non-PCI Single-Chip Full Duplex Ethernet Controller
TXEMPTY INTR
Write Acknowledge Reg. with
TXEMPTY Bit Set
Read TXEMPTY & TX INTR
TXEMPTY = 1
&
TXEMPTY = 0
&
TXEMPTY = X
&
TXINT = 0
TXINT = 0
TXINT = 1
(Everything went through
(Waiting for Completion)
(Transmission Failed)
successfully)
Read Pkt. # Register & Save
Write Address Pointer
Register
Read Status Word from RAM
Update Statistics
Update Variables
Issue "Release" Command
Acknowledge TXINTR
Re-Enable TXENA
Restore Packet Number
Return to ISR
Figure 8.4 – TXEMPTY INTR
(Assumes Auto Release Option Selected)
SMSC DS – LAN91C96I
Page 67
Rev. 11/18/2004
DATASHEET