Non-PCI Single-Chip Full Duplex Ethernet Controller
I/O SPACE - BANK0
OFFSET
NAME
MEMORY INFORMATION REGISTER
TYPE
READ ONLY
SYMBOL
MIR
8
For software compatibility with other LAN9000 parts all memory-related information is represented in 256 x
M byte units, where the multiplier M is determined by the MCR upper byte. M equals “1” for the
LAN91C96I.
FREE MEMORY AVAILABLE (in BYTES* 256* M)
0
0
0
0
0
1
1
0
0
0
0
0
MEMORY SIZE (in BYTES* 256* M)
0
1
1
0
FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free
memory. The register defaults to the MEMORY SIZE upon reset or upon the RESET MMU command.
MEMORY SIZE - This register can be read to determine the total memory size, and will always read 18H
(6144 bytes) for the LAN91C96I.
MEMORY SIZE REGISTER
M
1
1
ACTUAL MEMORY
64 kbytes
LAN91C90
LAN91C90
LAN91C92/
LAN91C94
LAN91C95
LAN91C96I
LAN91C100
FFH
40H
12H
16 kbytes
4608 bytes
1
18H
18H
FFH
1
1
2
6144 bytes
6144 bytes
128 kbytes
I/O SPACE - BANK0
OFFSET
NAME
TYPE
SYMBOL
MCR
A
MEMORY CONFIGURATION
lower byte READ/WRITE
upper byte READ ONLY
REGISTER
Memory Size Multiplier “M”
0
0
0
0
1
1
0
0
1
1
0
Memory Reserved for Transmit (in BYTES * 256 * M)
0
0
0
0
0
MEMORY RESERVED FOR TRANSMIT - Programming this value allows the host CPU to reserve
memory to be used later for transmit, limiting the amount of memory that receive packets can use up.
When programmed for zero, the memory allocation between transmit and receive is completely dynamic.
When programmed for a non-zero value, the allocation is dynamic if the free memory exceeds the
programmed value, while receive allocation requests are denied if the free memory is less or equal to the
programmed value. This register defaults to zero upon reset. It is not affected by the RESET MMU
command.
The value written to the MCR is a reserved memory space IN ADDITION TO ANY MEMORY
CURRENTLY IN USE. If the memory allocated for transmit plus the reserved space for transmit is required
to be constant (rather than grow with transmit allocations) the CPU should update the value of this register
after allocating or releasing memory.
SMSC DS – LAN91C96I
Page 41
Rev. 11/18/2004
DATASHEET
SMSC [ SMSC CORPORATION ]
