Non-PCI Single-Chip Full Duplex Ethernet Controller
INT SEL1-0 - In Local Bus mode, used to select one out of four interrupt pins. The three unused interrupts
are tristated.
INT SEL1
INT SEL0
INTERRUPT PIN USED
0
0
1
1
0
1
0
1
INTR0
INTR1
INTR2
INTR3
I/O SPACE - BANK1
OFFSET
2
NAME
TYPE
READ/WRITE
SYMBOL
BAR
BASE ADDRESS REGISTER
For Local Bus mode only, this register holds the I/O address decode option chosen for the I/O and ROM
space. It is part of the EEPROM saved setup, and is not usually modified during run-time.
A15
0
A14
0
ROM SIZE
A13
0
RA18
A9
1
RA17
A8
1
RA16
A7
0
RA15
A6
0
RA14
A5
0
0
1
1
0
0
1
1
1
A15 - A13 and A9 - A5 - These bits are compared in Local Bus mode against the I/O address on the bus to
determine the IOBASE for LAN91C96I registers. The 64k I/O space is fully decoded by the LAN91C96I
down to a 16 location space, therefore the unspecified address lines A4, A10, A11 and A12 must be all
zeros.
ROM SIZE - Determines the ROM decode area in Local Bus mode memory space as follows:
00 = ROM disable
01 = 16k: RA14-18 define ROM select.
10 = 32k: RA15-18 define ROM select.
11 = 64k: RA16-18 define ROM select.
RA18-RA14 - These bits are compared in Local Bus mode against the memory address on the bus to
determine if the ROM is being accessed, as a function of the ROM SIZE. ROM accesses are read only
memory accesses defined by MEMRD* going low.
For a full decode of the address space unspecified upper address lines have to be: A19 = "1", A20-A23
lines are not directly decoded, however Local Bus systems will only activate SMEMRD* only when A20-
A23=0.
All bits in this register are loaded from the serial EEPROM in Local Bus Mode only.
The I/O base decode defaults to 300h (namely, the high byte defaults to 18h). ROM SIZE defaults to 01.
ROM decode defaults to CC000 (namely the low byte defaults to 67h).
Below chart shows the decoding of I/O Base Address 300h:
SMSC DS – LAN91C96I
Page 43
Rev. 11/18/2004
DATASHEET
SMSC [ SMSC CORPORATION ]
