Non-PCI Single-Chip Full Duplex Ethernet Controller
TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the LAN91C96I
will complete the current transmission before stopping. When stopping due to an error, this bit is
automatically cleared.
Table 7.1 - Transmit Loop
FDS
E
TRANSMITS
AUI
FDUPLX
EPH_LOOP
LOOP
LOOPS AT
TO NETWORK
X
X
1
0
X
X
X
0
0
0
X
1
1
1
0
1
0
0
0
0
X
1
0
0
0
EPH Block
ENDEC
Cable
No
No
Yes
Yes
Yes
10BASE-T Driver
NORMAL CSMA/CD -
No Loopback
X
1
1
0
0
FULL DUPLEX
SWITCHED ETHERNET
- No loopback and No
SQET
Yes
I/O SPACE - BANK0
OFFSET
2
NAME
EPH STATUS REGISTER
TYPE
READ ONLY
SYMBOL
EPHSR
This register stores the status of the last transmitted frame. This register value, upon individual transmit
packet completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt
processing should use the copy in memory as the register itself will be updated by subsequent packet
transmissions. The register can be used for real time values (like TXENA and LINK OK). If TXENA is
cleared the register holds the last packet completion status.
TX
UNRN
0
TX
DEFR
0
LINK_
OK
0
LTX
BRD
0
CTR
_ROL
0
EXC
_DEF
0
LTX
MULT
0
LOST
CARR
0
MUL
COL
0
RES
0
LATCOL
WAKEUP
0
SNGL
COL
0
0
TX_SUC
0
SQET
0
16COL
0
TXUNRN - Transmit Under run. Set if Under run occurs, it also clears TXENA bit in TCR. Cleared by
setting TXENA high. This bit should never be set under normal operation.
LINK_OK - State of the 10BASE-T Link Integrity Test. A transition on the value of this bit generates an
interrupt when the LE ENABLE bit in the Control Register is set.
RES – This bit is reserved and will always return a zero(0). CTR_ROL - Counter Roll over. When set one
or more 4 bit counters have reached maximum count (15). Cleared by reading the ECR register.
EXC_DEF - Excessive deferral. When set last/current transmit was deferred for more than 1518 * 2 byte
times. Cleared at the end of every packet sent.
LOST_CARR - Lost carrier sense. When set indicates that Carrier Sense was not present at end of
preamble. Valid only if MON_CSN is enabled. This condition causes TXENA bit in TCR to be reset.
Cleared by setting TXENA bit in TCR.
SMSC DS – LAN91C96I
Page 37
Rev. 11/18/2004
DATASHEET
SMSC [ SMSC CORPORATION ]
