10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Figure 3.3 - LAN91C111 Physical Layer to Internal MAC Block Diagram ..................................................................12
Figure 7.1 - MI Serial Port Frame Timing Diagram.....................................................................................................23
Figure 7.2 - MII Frame Format & MII Nibble Order.....................................................................................................24
Figure 7.3 - TX/10BT Frame Format ..........................................................................................................................26
Figure 7.4 - TP Output Voltage Template - 10 MBPS ................................................................................................31
Figure 7.5 - TP Input Voltage Template -10MBPS .....................................................................................................34
Figure 7.6 - SOI Output Voltage Template - 10MBPS................................................................................................37
Figure 7.7 - Link Pulse Output Voltage Template - NLP, FLP ....................................................................................38
Figure 7.8 - NLP VS. FLP Link Pulse .........................................................................................................................39
Figure 8.1 - Data Frame Format.................................................................................................................................43
Figure 8.2 - Interrupt Structure ...................................................................................................................................64
Figure 10.1 - Interrupt Service Routine ......................................................................................................................85
Figure 10.2 - RX INTR ...............................................................................................................................................86
Figure 10.3 - TX INTR................................................................................................................................................87
Figure 10.4 - TXEMPTY INTR (Assumes Auto Release Option Selected).................................................................88
Figure 10.5 - Drive Send and Allocate Routines ........................................................................................................89
Figure 10.6 - Interrupt Generation for Transmit, Receive, MMU ................................................................................91
Figure 11.1 - 64 X 16 Serial EEPROM Map ...............................................................................................................94
Figure 12.1 - LAN91C111 on VL BUS........................................................................................................................97
Figure 12.2 - LAN91C111 on ISA BUS ......................................................................................................................99
Figure 12.3 - LAN91C111 on EISA BUS ..................................................................................................................101
Figure 14.1 - Asynchronous Cycle - nADS=0...........................................................................................................108
Figure 14.2 - Asynchronous Cycle - Using nADS.....................................................................................................109
Figure 14.3 - Asynchronous Cycle - nADS=0...........................................................................................................110
Figure 14.4 - Asynchronous Ready ..........................................................................................................................111
Figure 14.5 - Burst Write Cycles - nVLBUS=1 .........................................................................................................112
Figure 14.6 - Burst Read Cycles - nVLBUS=1 .........................................................................................................113
Figure 14.7 - Address Latching for All Modes ..........................................................................................................114
Figure 14.8 - Synchronous Write Cycle - nVLBUS=0...............................................................................................115
Figure 14.9 - Synchronous Read Cycle - nVLBUS=0...............................................................................................116
Figure 14.10 - MII Timing .........................................................................................................................................117
Figure 14.11 - Transmit Timing ................................................................................................................................118
Figure 14.12 - Receive Timing, End of Packet - 10 MBPS.......................................................................................119
Figure 14.13 - Collision Timing, Receive..................................................................................................................120
Figure 14.14 - Collision Timing, Transmit.................................................................................................................121
Figure 14.15 - Jam Timing .......................................................................................................................................122
Figure 14.16 - Link Pulse Timing..............................................................................................................................124
Figure 14.17 - FLP Link Pulse Timing ......................................................................................................................125
Figure 14.18 - 128 Pin TQFP Package Outline, 14X14X1.0 Body .............................................................................126
Figure 14.19 -128 Pin QFP Package Outline, 3.9 MM Footprint ..............................................................................127
LIST OF TABLES
Table 4.1 - LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package).............................................13
Table 7.1 - 4B/5B Symbol Mapping............................................................................................................................28
Table 7.2 - Transmit Level Adjust...............................................................................................................................32
Table 8.1 - Internal I/O Space Mapping .....................................................................................................................46
Table 9.1 - MII Serial Frame Structure .......................................................................................................................69
Table 9.2 - MII Serial Port Register MAP ...................................................................................................................71
Table 10.1 - Typical Flow Of Events For Placing Device In Low Power Mode ...........................................................80
Table 10.2 - Flow Of Events For Restoring Device In Normal Power Mode ...............................................................81
Table 12.1 - VL Local Bus Signal Connections ..........................................................................................................95
Table 12.2 - High-End ISA or Non-Burst EISA Machines Signal Connectors.............................................................98
Table 12.3 - EISA 32 Bit Slave Signal Connections ...................................................................................................99
Table 14.1 - Transmit Timing Characteristics...........................................................................................................117
Table 14.2 - Receive Timing Characteristics............................................................................................................118
Table 14.3 - Collision and Jam Timing Characteristics.............................................................................................119
Table 14.4 - Link Pulse Timing Characteristics ........................................................................................................123
Table 14.5 - 128 Pin TQFP Package Parameters ....................................................................................................126
Table 14.6 - 128 Pin QFP Package Parameters ......................................................................................................127
Rev. 1.4 (12-12-03)
Page 6
SMSC LAN91C111 Rev. B
DATASHEET
SMSC [ SMSC CORPORATION ]
