10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
TABLE OF CONTENTS
LAN91C111 Revisions .............................................................................................................................. 3
Chapter 1
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6
6.1
7.1
7.2
7.3
7.4
7.5
General Description ........................................................................................................... 7
Pin Configurations ............................................................................................................. 8
Block Diagrams ................................................................................................................ 10
Signal Descriptions........................................................................................................... 13
Description of Pin Functions ........................................................................................... 14
Signal Description Parameters........................................................................................ 19
Functional Description..................................................................................................... 20
DMA Block............................................................................................................................................20
Arbiter Block .........................................................................................................................................20
Buffer Types .................................................................................................................................... 19
Clock Generator Block .................................................................................................................... 20
CSMA/CD Block .............................................................................................................................. 20
7.2.1
7.2.2
Chapter 7
MMU Block ...................................................................................................................................... 21
BIU Block......................................................................................................................................... 21
MAC-PHY Interface......................................................................................................................... 21
7.5.1
7.5.2
7.5.3
7.5.4
Management Data Software Implementation........................................................................................22
Management Data Timing ....................................................................................................................22
MI Serial Port Frame Structure .............................................................................................................22
MII Packet Data Communication with External PHY.............................................................................24
7.6
7.7
Serial EEPROM Interface................................................................................................................ 25
Internal Physical Layer .................................................................................................................... 25
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
7.7.9
7.7.10
7.7.11
7.7.12
7.7.13
7.7.14
7.7.15
7.7.16
7.7.17
7.7.18
MII Disable............................................................................................................................................27
Encoder ................................................................................................................................................27
Decoder ................................................................................................................................................27
Clock and Data Recovery .....................................................................................................................28
Scrambler .............................................................................................................................................29
Descrambler .........................................................................................................................................29
Twisted Pair Transmitter .......................................................................................................................30
Twisted Pair Receiver ...........................................................................................................................33
Collision ................................................................................................................................................35
Start of Packet...................................................................................................................................35
End of Packet....................................................................................................................................36
Link Integrity & Autonegotiation.........................................................................................................37
Jabber ...............................................................................................................................................40
Receive Polarity Correction...............................................................................................................40
Full Duplex Mode ..............................................................................................................................41
Loopback...........................................................................................................................................41
PHY Powerdown ...............................................................................................................................42
PHY Interrupt ....................................................................................................................................42
7.8
8.1
8.2
8.3
8.4
8.5
8.6
Reset ............................................................................................................................................... 42
Chapter 8
MAC Data Structures and Registers.............................................................................. 43
Frame Format In Buffer Memory..................................................................................................... 43
Receive Frame Status..................................................................................................................... 44
I/O Space......................................................................................................................................... 45
Bank Select Register....................................................................................................................... 46
Bank 0 - Transmit Control Register................................................................................................. 47
Bank 0 - EPH Status Register......................................................................................................... 48
Rev. 1.4 (12-12-03)
Page 4
SMSC LAN91C111 Rev. B
DATASHEET
SMSC [ SMSC CORPORATION ]
