10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
8.7 Bank 0 - Receive Control Register.................................................................................................. 49
8.8 Bank 0 - Counter Register............................................................................................................... 50
8.9 Bank 0 - Memory Information Register ........................................................................................... 50
8.10
Bank 0 - Receive/Phy Control Register ....................................................................................... 51
8.11
Bank 1 - Configuration Register................................................................................................... 53
8.12
Bank 1 - Base Address Register.................................................................................................. 54
8.13
Bank 1 - Individual Address Registers......................................................................................... 54
8.14
Bank 1 - General Purpose Register............................................................................................. 55
8.15
Bank 1 - Control Register............................................................................................................. 55
8.16
Bank 2 - MMU Command Register .............................................................................................. 56
8.17
Bank 2 - Packet Number Register ............................................................................................... 58
8.18
Bank 2 - FIFO Ports Register....................................................................................................... 59
8.19
Bank 2 - Pointer Register............................................................................................................. 59
8.20
Bank 2 - Data Register................................................................................................................. 60
8.21
Bank 2 - Interrupt Status Registers.............................................................................................. 61
8.22
Bank 3 - Multicast Table Registers .............................................................................................. 65
8.23
Bank 3 - Management Interface................................................................................................... 66
8.24
Bank 3 - Revision Register .......................................................................................................... 66
8.25
Bank 3 - Early RCV Register ....................................................................................................... 67
8.26
Bank 7 - External Registers ......................................................................................................... 67
Chapter 9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
10.1
10.2
10.3
10.4
PHY MII Registers........................................................................................................... 68
Register 0. Control Register............................................................................................................ 72
Register 1. Status Register ............................................................................................................. 73
Register 2&3. PHY Identifier Register............................................................................................. 74
Register 4. Auto-Negotiation Advertisement Register .................................................................... 74
Register 5. Auto-Negotiation Remote End Capability Register ...................................................... 76
Register 16. Configuration 1- Structure and Bit Definition .............................................................. 76
Register 17. Configuration 2 - Structure and Bit Definition ............................................................. 77
Register 18. Status Output - Structure and Bit Definition................................................................ 77
Register 19. Mask - Structure and Bit Definition ............................................................................ 78
Register 20. Reserved - Structure and Bit Definition.................................................................. 79
Chapter 10
Software Driver and Hardware Sequence Flow......................................................... 80
Software Driver and Hardware Sequence Flow for Power Management.................................... 80
Typical Flow of Events for Transmit (Auto Release = 0) ............................................................. 81
Typical Flow of Events for Transmit (Auto Release = 1) ............................................................. 83
Typical Flow of Event For Receive .............................................................................................. 84
Chapter 11
Chapter 12
Chapter 13
13.1
13.2
13.3
13.4
Board Setup Information ............................................................................................. 92
Application Considerations.......................................................................................... 95
Operational Description ............................................................................................. 102
Maximum Guaranteed Ratings*................................................................................................. 102
DC Electrical Characteristics ..................................................................................................... 102
Twisted Pair Characteristics, Transmit ...................................................................................... 105
Twisted Pair Characteristics, Receive ....................................................................................... 106
Chapter 14
Timing Diagrams ........................................................................................................ 108
LIST OF FIGURES
Figure 2.1 - Pin Configuration - LAN91C111-FEAST 128 PIN TQFP...........................................................................8
Figure 2.2 - Pin Configuration - LAN91C111-FEAST 128 PIN QFP.............................................................................9
Figure 3.1 - Basic Functional Block Diagram .............................................................................................................10
Figure 3.2 - Block Diagram.........................................................................................................................................11
SMSC LAN91C111 Rev. B
Page 5
Rev. 1.4 (12-12-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
