High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
A[7:1]
nCS, nWR
Data Bus
Figure 6.5 PIO Write Cycle Timing
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Table 6.7 PIO Write Cycle Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
Write Cycle Time
45
32
13
0
ns
ns
ns
ns
ns
ns
ns
cycle
t
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address Setup to nCS, nWR Assertion
Address Hold Time
csl
t
csh
asu
t
t
0
ah
t
Data Setup to nCS, nWR Deassertion
Data Hold Time
7
dsu
t
0
dh
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
6.7
TX Data FIFO Direct PIO Writes
In this mode the upper address inputs are not decoded, and any write to the LAN9118 will write the
TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is
normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9118. Timing is
identical to a PIO write, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Timing for 16-bit and 32-bit cycles is identical with the exception that D[31:16] is ignored during a 16-
bit write. Note that address lines A[2:1] are still used when the LAN9118 is operating in 32-bit and 16-
bit mode. Address bits A[7:3] are ignored.
SMSC LAN9118
119
Revision 1.3 (05-31-07)
DATASHEET
SMSC [ SMSC CORPORATION ]
