High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 6.3 PIO Read Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
Read Cycle Time
45
32
13
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycle
t
nCS, nRD Assertion Time
csl
t
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Setup to nCS, nRD Valid
Address Hold Time
csh
t
30
csdv
t
0
0
0
asu
t
ah
t
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
don
t
7
doff
doh
t
0
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
6.3
PIO Burst Reads
In this mode, performance is improved by allowing up to 8, DWORD read cycles, or 16, WORD read
cycles back-to-back. PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable
(nRD). Either or both of these control signals must go high between bursts for the period specified.
Timing for 16-bit and 32-bit PIO Burst Mode Read cycles is identical, with the exception that D[31:16]
are not driven during a 16-bit burst.
A[7:5]
A[4:1]
nCS, nRD
Data Bus
Figure 6.2 LAN9118 PIO Burst Read Cycle Timing
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
SMSC LAN9118
115
Revision 1.3 (05-31-07)
DATASHEET
SMSC [ SMSC CORPORATION ]
