High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 6.4 PIO Burst Read Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
13
ns
ns
csh
t
t
30
csdv
acyc
45
0
t
Address Setup to nCS, nRD valid
Address Stable to Data Valid
Address Hold Time
ns
asu
adv
t
40
7
t
0
0
ns
ns
ns
ns
ah
t
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
don
t
doff
doh
t
0
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
6.4
RX Data FIFO Direct PIO Reads
In this mode the upper address inputs are not decoded, and any read of the LAN9118 will read the
RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is
normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9118. Timing is
identical to a PIO read, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Timing for 16-bit and 32-bit Direct PIO Read cycles is identical with the exception that D[31:16] is not
driven during a 16-bit read. Note that address lines A[2:1] are still used, and address bits A[7:3] are
ignored.
FIFO_SEL
A[2:1]
nCS, nRD
Data Bus
Figure 6.3 RX Data FIFO Direct PIO Read Cycle Timing
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Revision 1.3 (05-31-07)
116
SMSC LAN9118
DATASHEET
SMSC [ SMSC CORPORATION ]
