High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
6.8
Reset Timing
T6.1
nRST
T6.2
T6.3
Configuration
signals
T6.4
Output drive
Table 6.9 Reset Timing
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNITS
NOTES
T6.1
T6.2
Reset Pulse Width
200
200
us
ns
Configuration input setup to
nRST rising
T6.3
T6.4
Configuration input hold after
nRST rising
10
ns
ns
Output Drive after nRST rising
16
6.9
EEPROM Timing
The following specifies the EEPROM timing requirements for the LAN9118
Figure 6.7 EEPROM Timing
SMSC LAN9118
121
Revision 1.3 (05-31-07)
DATASHEET