High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 6.2 Read After Read Timing Rules
OR PERFORM THIS MANY
READS OF BYTE_TEST…
(ASSUMING Tcycle OF 45NS)
AFTER
READING...
WAIT FOR THIS MANY
NS…
BEFORE READING...
RX Data FIFO
RX Status FIFO
TX Status FIFO
RX_DROP
135
135
135
180
3
3
3
4
RX_FIFO_INF
RX_FIFO_INF
TX_FIFO_INF
RX_DROP
6.2
PIO Reads
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
PIO reads are supported for both 16- and 32-bit access. Timing for 16-bit and 32-bit PIO Read cycles
is identical with the exception that D[31:16] are not driven during a 16-bit read.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read
cycles.
A[7:1]
nCS, nRD
Data Bus
Figure 6.1 LAN9118 PIO Read Cycle Timing
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Revision 1.3 (05-31-07)
114
SMSC LAN9118
DATASHEET
SMSC [ SMSC CORPORATION ]
