Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
BITS
DESCRIPTION
TYPE
DEFAULT
15-0
RX Data FIFO Used Space (RXDUSED).). Reads the amount of space in
bytes, used in the RX data FIFO. For each receive frame, this field is
incremented by the length of the receive data rounded up to the nearest
DWORD (if the payload does not end on a DWORD boundary).
RO
0000h
5.3.12
TX_FIFO_INF—Transmit FIFO Information Register
Offset:
80h
Size:
32 bits
This register contains the free space in the transmit data FIFO and the used space in the transmit
status FIFO in the LAN9116.
BITS
31-24
23-16
DESCRIPTION
Reserved
TYPE
RO
DEFAULT
-
TX Status FIFO Used Space (TXSUSED). Indicates the amount of space
RO
00h
in DWORDS used in the TX Status FIFO.
15-0
TX Data FIFO Free Space (TDFREE). Reads the amount of space in bytes,
available in the TX data FIFO. The application should never write more data
than is available, as indicated by this value.
RO
1200h
5.3.13
PMT_CTRL— Power Management Control Register
Offset:
84h
Size:
32 bits
This register controls the Power Management features. This register can be read while the
LAN9116 is in a power saving mode.
Note: The LAN9116 must always be read at least once after power-up, reset, or upon return from a
power-saving state or write operations will not function.
SMSC LAN9116
Revision 1.1 (05-17-05)
DATA7S9HEET
SMSC [ SMSC CORPORATION ]
