Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.3.14
GPIO_CFG—General Purpose IO Configuration Register
Offset:
88h
Size:
32 bits
This register configures the GPIO and LED functions.
Bits
31
Description
Type
RO
Default
Reserved
-
30:28
LED[3:1] enable (LEDx_EN). A ‘1’ sets the associated pin as an LED output.
When cleared low, the pin functions as a GPIO signal.
LED1/GPIO0 – bit 28
R/W
000
LED2/GPIO1 – bit 29
LED3/GPIO2 – bit 30
27
Reserved
RO
-
26:24
GPIO Interrupt Polarity 0-2 (GPIO_INT_POL). When set high, a high logic
level on the corresponding GPIO pin will set the corresponding INT_STS
register bit. When cleared low, a low logic level on the corresponding GPIO
pin will set the corresponding INT_STS register bit.
R/W
000
GPIO Interrupts must also be enabled in GPIOx_INT_EN in the INT_EN
register.
GPIO0 – bit 24
GPIO1 – bit 25
GPIO2 – bit 26
Note:
GPIO inputs must be active for greater than 40nS to be recognized
as interrupt inputs.
23
Reserved
RO
-
22:20
EEPROM Enable (EEPR_EN). The value of this field determines the function
of the external EEDIO and EECLK:
R/W
000
Please refer to Table 5.4 for the EEPROM Enable bit function definitions.
Note:
The host must not change the function of the EEDIO and EECLK
pins when an EEPROM read or write cycle is in progress. Do not
use reserved settings.
19
Reserved
RO
-
18:16
GPIO Buffer Type 0-2 (GPIOBUFn). When set, the output buffer for the
R/W
000
corresponding GPIO signal is configured as a push/pull driver. When cleared,
the corresponding GPIO set configured as an open-drain driver.
GPIO0 – bit 16
GPIO1 – bit 17
GPIO2 – bit 18
15:11
10:8
Reserved
RO
-
GPIO Direction 0-2 (GPDIRn). When set, enables the corresponding GPIO
R/W
0000
as output. When cleared the GPIO is enabled as an input.
GPIO0 – bit 8
GPIO1 – bit 9
GPIO2 – bit 10
7:5
4:3
Reserved
RO
-
GPO Data 3-4 (GPODn). The value written is reflected on GPOn.
R/W
00
GPO3 – bit 3
GPO4 – bit 4
Revision 1.1 (05-17-05)
SMSC LAN9116
DATA8S2HEET
SMSC [ SMSC CORPORATION ]
