Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Bits
Description
Type
Default
2:0
GPIO Data 0-2 (GPIODn). When enabled as an output, the value written is
R/W
000
reflected on GPIOn. When read, GPIOn reflects the current state of the
corresponding GPIO pin.
GPIO0 – bit 0
GPIO1 – bit 1
GPIO2 – bit 2
Table 5.4 EEPROM Enable Bit Definitions
[22]
[21]
[20]
EEDIO FUNCTION
EECLK FUNCTION
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EEDIO
GPO3
EECLK
GPO4
Reserved
Reserved
GPO3
RX_DV
TX_EN
TX_EN
TX_CLK
GPO4
RX_DV
RX_CLK
5.3.15
GPT_CFG-General Purpose Timer Configuration Register
Offset:
8Ch
Size:
32 bits
This register configures the General Purpose timer. The GP Timer can be configured to generate host
interrupts at intervals defined in this register.
BITS
DESCRIPTION
Reserved
TYPE
DEFAULT
31-30
RO
-
29
GP Timer Enable (TIMER_EN). When a one is written to this bit the GP
Timer is put into the run state. When cleared, the GP Timer is halted. On
the 1 to 0 transition of this bit the GPT_LOAD field will be preset to FFFFh.
R/W
0
28-16
15-0
Reserved
RO
-
General Purpose Timer Pre-Load (GPT_LOAD). This value is pre-loaded
R/W
FFFFh
into the GP-Timer.
SMSC LAN9116
Revision 1.1 (05-17-05)
DATA8S3HEET
SMSC [ SMSC CORPORATION ]
