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LAN9116 参数 Datasheet PDF下载

LAN9116图片预览
型号: LAN9116
PDF下载: 下载PDF文件 查看货源
内容描述: 高效的单芯片10/100非PCI以太网控制器 [Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller]
分类和应用: 控制器PC以太网局域网(LAN)标准
文件页数/大小: 126 页 / 1500 K
品牌: SMSC [ SMSC CORPORATION ]
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller  
Datasheet  
BITS  
15-14  
13-12  
DESCRIPTION  
Reserved  
TYPE  
RO  
DEFAULT  
-
Threshold Control Bits (TR). These control the transmit threshold values  
the MIL should use. These bits are used when the SF bit is reset. The host  
can program the Transmit threshold by setting these bits. The intent is to  
allow the MIL to transfer data to the final destination only after the threshold  
value is met.  
R/W  
00  
In 10Mbps mode (TTM = 1) the threshold is set as follows:  
[13]  
0
[12]  
0
Threshold (DWORDS)  
012h  
018h  
020h  
028h  
0
1
1
0
1
1
In 100Mbps mode (TTM = 0) the threshold is set by as follows:  
[13]  
0
[12]  
0
Threshold (DWORDS)  
020h  
040h  
080h  
100h  
0
1
1
0
1
1
11-3  
2
Reserved  
RO  
RO  
-
-
32/16-bit Mode. When set, the LAN9116 is set for 32-bit operation. When  
clear, it is configured for 16-bit operation. This field is the value of the  
D32/nD16 strap.  
1
0
Soft Reset Time-out (SRST_TO). If a software reset is attempted when the  
internal PHY is not in the operational state (RX_CLK and TX_CLK running),  
the reset will not complete and the soft reset operation will time-out and this  
bit will be set to a ‘1’. The host processor must correct the problem and  
issue another soft reset.  
RO  
SC  
0
0
Soft Reset (SRST). Writing 1 generates a software initiated reset. This reset  
generates a full reset of the MAC CSR’s. The SCSR’s (system command  
and status registers) are reset except for any NASR bits. Soft reset also  
clears any TX or RX errors (TXE/RXE). This bit is self-clearing.  
Notes:  
Do not attempt a soft reset unless the internal PHY is fully awake and  
operational. After a PHY reset, or when returning from a reduced power  
state, the PHY must be given adequate time to return to the operational  
state before a soft reset can be issued. The internal RX_CLK and TX_CLK  
signals must be running for a proper software reset. Please refer to  
Section 6.8, "Reset Timing," on page 119 for details on PHY reset timing.  
The LAN9116 must always be read at least once after power-up, reset, or  
upon return from a power-saving state or write operations will not function.  
Revision 1.1 (05-17-05)  
SMSC LAN9116  
DATA7S6HEET  
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