±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR® Technology in a Small Footprint
Datasheet
4.6.2
RMII
The SMSC LAN8700/LAN8700i supports the low pin count Reduced Media Independent Interface
(RMII) intended for use between Ethernet PHYs and Switch ASICs. Under IEEE 802.3, an MII
comprised of 16 pins for data and control is defined. In devices incorporating many MACs or PHY
interfaces such as switches, the number of pins can add significant cost as the port counts increase.
The management interface (MDIO/MDC) is identical to MII. The RMII interface has the following
characteristics:
It is capable of supporting 10Mb/s and 100Mb/s data rates
A single clock reference is sourced from the MAC to PHY (or from an external source)
It provides independent 2 bit wide (di-bit) transmit and receive data paths
It uses LVCMOS signal levels, compatible with common digital CMOS ASIC processes
The RMII includes 6 interface signals with one of the signals being optional:
transmit data - TXD[1:0]
transmit strobe - TX_EN
receive data - RXD[1:0]
receive error - RX_ER (Optional)
carrier sense - CRS_DV
Reference Clock - CLKIN/XTAL1 (RMII references usually define this signal as REF_CLK)
4.6.2.1
Reference Clock
The Reference Clock - CLKIN, is a continuous clock that provides the timing reference for CRS_DV,
RXD[1:0], TX_EN, TXD[1:0], and RX_ER. The Reference Clock is sourced by the MAC or an external
source. Switch implementations may choose to provide REF_CLK as an input or an output depending
on whether they provide a REF_CLK output or rely on an external clock distribution device.
The “Reference Clock” frequency must be 50 MHz ± 50 ppm with a duty cycle between 40% and 60%
inclusive. The SMSC LAN8700/LAN8700i uses the “Reference Clock” as the network clock such that
no buffering is required on the transmit data path. The SMSC LAN8700/LAN8700i will recover the clock
from the incoming data stream, the receiver will account for differences between the local REF_CLK
and the recovered clock through use of sufficient elasticity buffering. The elasticity buffer does not
affect the Inter-Packet Gap (IPG) for received IPGs of 36 bits or greater. To tolerate the clock variations
specified here for Ethernet MTUs, the elasticity buffer shall tolerate a minimum of ±10 bits.
4.6.2.2
CRS_DV - Carrier Sense/Receive Data Valid
The CRS_DV is asserted by the LAN8700/LAN8700i when the receive medium is non-idle. CRS_DV
is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode.
That is, in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 non-contiguous
zeroes in 10 bits are detected, carrier is said to be detected.
Loss of carrier shall result in the deassertion of CRS_DV synchronous to the cycle of REF_CLK which
presents the first di-bit of a nibble onto RXD[1:0] (i.e. CRS_DV is deasserted only on nibble
boundaries). If the LAN8700/LAN8700i has additional bits to be presented on RXD[1:0] following the
initial deassertion of CRS_DV, then the LAN8700/LAN8700i shall assert CRS_DV on cycles of
REF_CLK which present the second di-bit of each nibble and de-assert CRS_DV on cycles of
REF_CLK which present the first di-bit of a nibble. The result is: Starting on nibble boundaries
CRS_DV toggles at 25 MHz in 100Mb/s mode and 2.5 MHz in 10Mb/s mode when CRS ends before
RX_DV (i.e. the FIFO still has bits to transfer when the carrier event ends.) Therefore, the MAC can
accurately recover RX_DV and CRS.
During a false carrier event, CRS_DV shall remain asserted for the duration of carrier activity. The data
on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV
SMSC LAN8700/LAN8700i
Revision 2.3 (04-12-11)
DATA2S7HEET
SMSC [ SMSC CORPORATION ]
