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LAN8700IC-AEZG 参数 Datasheet PDF下载

LAN8700IC-AEZG图片预览
型号: LAN8700IC-AEZG
PDF下载: 下载PDF文件 查看货源
内容描述: [LAN Controller, 4 Channel(s), 12.5MBps, CMOS, 6 X 6 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, QFN-36]
分类和应用: 通信时钟局域网数据传输外围集成电路
文件页数/大小: 83 页 / 687 K
品牌: SMSC [ SMSC CORPORATION ]
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±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR® Technology in a Small Footprint  
Datasheet  
J
K
5
5
5
D
Idle  
data data data data  
T
R
CLEAR-TEXT  
RX_CLK  
RX_DV  
5
5
5
5
5
D
data data data data  
RXD  
Figure 4.3 Relationship Between Received Data and Specific MII Signals  
4.3.8  
4.3.9  
Receiver Errors  
During a frame, unexpected code-groups are considered receive errors. Expected code groups are the  
DATA set (0 through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the RX_ER  
signal is asserted and arbitrary data is driven onto the RXD[3:0] lines. Should an error be detected  
during the time that the /J/K/ delimiter is being decoded (bad SSD error), RX_ER is asserted true and  
the value ‘1110’ is driven onto the RXD[3:0] lines. Note that the Valid Data signal is not yet asserted  
when the bad SSD error occurs.  
100M Receive Data Across the MII/RMII Interface  
In MII mode, the 4-bit data nibbles are sent to the MII block. These data nibbles are clocked to the  
controller at a rate of 25MHz. The controller samples the data on the rising edge of RX_CLK. To ensure  
that the setup and hold requirements are met, the nibbles are clocked out of the PHY on the falling  
edge of RX_CLK. RX_CLK is the 25MHz output clock for the MII bus. It is recovered from the received  
data to clock the RXD bus. If there is no received signal, it is derived from the system reference clock  
(CLKIN).  
When tracking the received data, RX_CLK has a maximum jitter of 0.8ns (provided that the jitter of the  
input clock, CLKIN, is below 100ps).  
In RMII mode, the 2-bit data nibbles are sent to the RMII block. These data nibbles are clocked to the  
controller at a rate of 50MHz. The controller samples the data on the rising edge of CLKIN/XTAL1  
(REF_CLK). To ensure that the setup and hold requirements are met, the nibbles are clocked out of  
the PHY on the falling edge of CLKIN/XTAL1 (REF_CLK).  
4.4  
10Base-T Transmit  
Data to be transmitted comes from the MAC layer controller. The 10Base-T transmitter receives 4-bit  
nibbles from the MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream. The data  
stream is then Manchester-encoded and sent to the analog transmitter, which drives a signal onto the  
twisted pair via the external magnetics.  
The 10M transmitter uses the following blocks:  
„
„
„
„
MII (digital)  
TX 10M (digital)  
10M Transmitter (analog)  
10M PLL (analog)  
4.4.1  
10M Transmit Data Across the MII/RMII Interface  
The MAC controller drives the transmit data onto the TXD BUS. For MII, when the controller has driven  
TX_EN high to indicate valid data, the data is latched by the MII block on the rising edge of TX_CLK.  
The data is in the form of 4-bit wide 2.5MHz data.  
Revision 2.3 (04-12-11)  
SMSC LAN8700/LAN8700i  
DATA2S4HEET