±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR® Technology in a Small Footprint
Datasheet
In Full Duplex mode, the PHY is able to transmit and receive data simultaneously. In this mode, CRS
responds only to receive activity. The CSMA/CD protocol does not apply and collision detection is
disabled.
4.8
HP Auto-MDIX
HP Auto-MDIX facilitates the use of CAT-3 (10 Base-T) or CAT-5 (100 Base-T) media UTP interconnect
cable without consideration of interface wiring scheme. If a user plugs in either a direct connect LAN
cable, or a cross-over patch cable, as shown in Figure 4.4 on page 31, the SMSC LAN8700/LAN8700i
Auto-MDIX PHY is capable of configuring the TXP/TXN and RXP/RXN pins for correct transceiver
operation.
The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX
and TX line pairs are interchangeable, special PCB design considerations are needed to accommodate
the symmetrical magnetics and termination of an Auto-MDIX design.
The Auto-MDIX function can be disabled through an internal register.
Figure 4.4 Direct Cable Connection vs. Cross-over Cable Connection.
4.9
Internal +1.8V Regulator Disable
One feature of the flexPWR technology is the ability to configure the internal 1.8V regulator off. When
the regulator is disabled, external 1.8V must be supplied to VDD_CORE. This makes it possible to
reduce total system power, since an external switching regulator with greater efficiency than the
internal linear regulator may be used to provide the +1.8V to the PHY circuitry.
4.9.1
Disable the Internal +1.8V Regulator
To disable the +1.8V internal regulator, a pullup strapping resistor (see Table 4.3, “Boot Strapping
Configuration Resistors,” on page 33) is connected from RXCLK/REGOFF to VDDIO. At power-on,
after both VDDIO and VDDA are within specification, the PHY will sample the RXCLK/REGOFF pin to
determine if the internal regulator should turn on. If the pin is sampled at a voltage greater than VIH,
then the internal regulator is disabled, and the system must supply +1.8V to the VDD_CORE pin. The
voltage at VDD33 must be at least 2.64V (0.8 * 3.3V) before voltage is applied to VDD_CORE. As
described in Section 4.9.2, when the RXCLK/REGOFF pin is left floating or connected to VSS, then
the internal regulator is enabled and the system does not supply +1.8V to the VDD_CORE pin.
SMSC LAN8700/LAN8700i
Revision 2.3 (04-12-11)
DATA3S1HEET
SMSC [ SMSC CORPORATION ]
