High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Table 6.6 Configuration Inputs (continued)
PIN NO.
NAME
BUFFER TYPE
VIH
VIL
IOH
IOL
VOL
VOH
12
1
REG_EN
MII
APAD
BPL8H4
-4 mA
+8 mA
+0.4 V
VDD –
+0.4 V
Table 6.7 General Signals
PIN NO.
NAME
BUFFER TYPE
VIH
VIL
IOH
IOL
VOL
VOH
1
GPO0
BPL8H4
-4 mA
+8 mA
+0.4 V
VDD –
+0.4 V
2
3
GPO1
GPO2
nINT
BPL8H4
BPL8H4
-4 mA
-4 mA
-4 mA
+8 mA
+8 mA
+8 mA
+0.4 V
+0.4 V
+0.4 V
VDD –
+0.4 V
VDD –
+0.4 V
46
BPL8H4 /
VDD –
+0.4 V
OPEN DRAIN
25
23
22
64
nRST
CLKIN/XTAL1
XTAL2
DS1116
OSCIN
OSCOUT
N/A
NC1
Table 6.8 Analog References
PIN NO.
NAME
BUFFER TYPE
VIH
VIL
IOH
IOL
VOL
VOH
59
56
EXRES1
NC2
AI
AI/O
Table 6.9 Internal Pull-Up / Pull-/Down Configurations
PIN NO.
NAME
PULL-UP OR PULL-DOWN
TYPE
1
2
GPO0/MII
GPO1/PHYAD4
MODE0
Pull-down
Pull-up
30 uA
30 uA
30 uA
30 uA
30 uA
30 uA
30 uA
4
Pull-up
5
MODE1
Pull-up
6
MODE2
Pull-up
9
TEST0
Pull-down
Pull-down
10
TEST1
SMSC LAN83C185
Rev. 0.6 (12-12-03)
DATA5S5HEET
SMSC [ SMSC CORPORATION ]
