High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
6.5.3
DC Characteristics - Input and Output Buffers
Table 6.3 MII BUS INTERFACE SIGNALS
PIN NO.
NAME
BUFFER TYPE
VIH
VIL
IOH
IOL
VOL
VOH
41
42
44
45
37
39
38
TXD0
TXD1
INBUFD2
INBUFD2
INBUFD2
INBUFD2
INBUFD2
INBUFD2
BPL8H8
+2.0 V
+2.0 V
+2.0 V
+2.0 V
+2.0 V
+2.0 V
+0.8 V
+0.8 V
+0.8 V
+0.8 V
+0.8 V
+0.8 V
TXD2
TXD3
TX_ER/TXD4
TX_EN
TX_CLK
-8 mA
-8 mA
-8 mA
-8 mA
-8 mA
-8 mA
-8 mA
-8 mA
-8 mA
-8 mA
+8 mA
+8 mA
+8 mA
+8 mA
+8 mA
+8 mA
+8 mA
+8 mA
+8 mA
+8 mA
+0.4 V
+0.4 V
+0.4 V
+0.4 V
+0.4 V
+0.4 V
+0.4 V
+0.4 V
+0.4 V
+0.4 V
VDD –
+0.4 V
32
31
30
29
35
33
34
48
47
RXD0
RXD1
BPL8H8
BPL8H8
BPL8H8
BPL8H8
BPL8H8
BPL8H8
BPL8H8
BPL8H8
BPL8H8
VDD –
+0.4 V
VDD –
+0.4 V
RXD2
VDD –
+0.4 V
RXD3
VDD –
+0.4 V
RX_ER/RXD4
RX_DV
RX_CLK
CRS
VDD –
+0.4 V
VDD –
+0.4 V
VDD –
+0.4 V
VDD –
+0.4 V
COL
VDD –
+0.4 V
27
26
MDC
INBUFD2
BPL8H8
+2.0 V
+0.8 V
MDIO
-8 mA
+8 mA
+0.4 V
VDD –
+0.4 V
SMSC LAN83C185
Rev. 0.6 (12-12-03)
DATA5S3HEET
SMSC [ SMSC CORPORATION ]
