DATA and ecpAFifo PORT
ADDRESS OFFSET = 00H
BIT 4 Select
The level on the Select input is read by the CPU
as bit 4 of the Device Status Register.
Modes 000 and 001 (Data Port)
BIT 5 PError
The Data Port is located at an offset of '00H'
from the base address. The data register is
cleared at initialization by RESET. During a
WRITE operation, the Data Register latches the
contents of the data bus on the rising edge of
the nIOW input. The contents of this register
are buffered (non inverting) and output onto the
PD0-PD7 ports. During a READ operation,
PD0-PD7 ports are read and output to the host
CPU.
The level on the PError input is read by the CPU
as bit 5 of the Device Status Register. Printer
Status Register.
BIT 6 nAck
The level on the nAck input is read by the CPU
as bit 6 of the Device Status Register.
BIT 7 nBusy
The complement of the level on the BUSY input
is read by the CPU as bit 7 of the Device Status
Register.
Mode 011 (ECP FIFO - Address/RLE)
A data byte written to this address is placed in
the FIFO and tagged as an ECP Address/RLE.
The hardware at the ECP port transmits this
DEVICE CONTROL REGISTER (dcr)
ADDRESS OFFSET = 02H
byte to the peripheral automatically.
The
The Control Register is located at an offset of
'02H' from the base address. The Control
Register is initialized to zero by the RESET
input, bits 0 to 5 only being affected; bits 6 and
7 are hard wired low.
operation of this register is only defined for the
forward direction (direction is 0). Refer to the
ECP Parallel Port Forward Timing Diagram,
located in the Timing Diagrams section of this
data sheet .
BIT 0 STROBE - STROBE
This bit is inverted and output onto the
nSTROBE output.
DEVICE STATUS REGISTER (dsr)
ADDRESS OFFSET = 01H
The Status Port is located at an offset of '01H'
BIT 1 AUTOFD - AUTOFEED
from the base address.
Bits 0-2 are not
This bit is inverted and output onto the
nAUTOFD output. A logic “1” causes the printer
to generate a line feed after each line is printed.
A logic “0” means no autofeed.
implemented as register bits, during a read of
the Printer Status Register these bits are a low
level. The bits of the Status Port are defined as
follows:
BIT 2 nINIT - nINITIATE OUTPUT
This bit is output onto the nINIT output without
inversion.
BIT 3 nFault
The level on the nFault input is read by the CPU
as bit 3 of the Device Status Register.
BIT 3 SELECTIN
This bit is inverted and output onto the nSLCTIN
output. A logic “1” on this bit selects the printer;
a logic 0 means the printer is not selected.
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