cnfgA (Configuration Register A)
ADDRESS OFFSET = 400H
Mode = 111
BIT 4 nErrIntrEn
Read/Write (Valid only in ECP Mode)
1: Disables the interrupt generated on the
asserting edge of nFault.
0: Enables an interrupt pulse on the high to
low edge of nFault. Note that an interrupt
will be generated if nFault is asserted
(interrupting) and this bit is written from a 1
to a 0. This prevents interrupts from being
lost in the time between the read of the ecr
and the write of the ecr.
This register is a read-only register. When read,
10H is returned. This indicates to the system
that this is an 8-bit implementation. (PWord = 1
byte)
cnfgB (Configuration Register B)
ADDRESS OFFSET = 401H
Mode = 111
BIT 3 dmaEn
Read/Write
BIT 7 compress
1: Enables DMA (DMA starts when serviceIntr
is 0).
0: Disables DMA unconditionally.
This bit is read only. During a read it is a low
level. This means that this chip does not
support hardware RLE compression. It does
support hardware de-compression!
BIT 2 serviceIntr
Read/Write
BIT 6 intrValue
1: Disables DMA and all of the service
interrupts.
Returns the value on the ISA IRQ line to
determine possible conflicts.
0: Enables one of the following three cases of
interrupts. Once one of the three service
interrupts has occurred serviceIntr bit shall
be set to a “1” by hardware. It must be reset
to “0” to re-enable the interrupts. Writing
this bit to a “1” will not cause an interrupt.
case dmaEn=1:
BITS [3:0] Parallel Port IRQ
Refer to Table 44B.
BITS [2:0] Parallel Port DMA
Refer to Table 44C.
During DMA (this bit is set to a “1” when
terminal count is reached).
case dmaEn=0 direction=0:
ecr (Extended Control Register)
ADDRESS OFFSET = 402H
Mode = all
This register controls the extended ECP parallel
port functions.
This bit shall be set to “1” whenever there
are writeIntrThreshold or more bytes free in
the FIFO.
case dmaEn=0 direction=1:
BIT 7-5
This bit shall be set to “1” whenever there
are readIntrThreshold or more valid bytes to
be read from the FIFO.
These bits are Read/Write and select the Mode.
101
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