Table 56 shows the baud rates possible with a 1.8462 MHz clock.
Table 56 - Baud Rates Using 1.8462 MHz Clock
DIVISOR USED TO
GENERATE 16X
CLOCK
DESIRED
BAUD RATE
50
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL*
0.03
CROC:
BIT 7 OR 6
X
2307
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
230400
460800
1538
1049
858
769
384
192
96
64
58
48
32
24
16
12
6
3
2
1
0.03
0.005
0.01
0.03
0.16
0.16
0.16
0.16
0.5
0.16
0.16
0.16
0.16
0.16
0.16
0.16
1.6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0.16
0.16
0.16
32770
32769
1
SMSC DS – FDC37N769
Page 68 of 138
Rev. 12/21/2000