DMAEN, Bit 3
PC/AT and Model 30 Interface Mode
In PC/AT and Model 30 mode writing this bit to logic “1” will enable the DRQ, nDACK, TC and FINTR outputs. This
bit being a logic “0” will disable the nDACK and TC inputs, and hold the DRQ and FINTR outputs in a high impedance
state. In PC/AT and Model 30 mode the DMAEN bit is a logic “0” after a reset.
PS/2 Interface Mode
In PS/2 mode the DRQ, nDACK, TC and FINTR pins are always enabled. During a reset the DRQ, nDACK, TC, and
FINTR pins will remain enabled, but the DMAEN bit will be cleared to a logic “0”.
MOTOR ENABLE 0, Bit 4
This bit controls the MTR0 disk interface output. A logic “1” in this bit will cause the output pin to go active.
MOTOR ENABLE 1, Bit 5
This bit controls the MTR1 disk interface output. A logic “1” in this bit will cause the output pin to go active.
MOTOR ENABLE 2, Bit 6
The MOTOR ENABLE 2 bit controls the MTR2 disk interface output. A logic “1” in this bit will cause the output pin to
go active.
MOTOR ENABLE 3, Bit 7
The MOTOR ENABLE 3 bit controls the MTR3 disk interface output. A logic “1” in this bit causes the output to go
active.
Table 10 - Drive Activation Values
DRIVE
DOR VALUE
1CH
0
1
2
3
2DH
4EH
8FH
Drive Select Encoding
The FDC37N769 can support two types of drive select encoding: Internal 2 Drive decoding (Table 11) and External 2-
to-4 Drive decoding (Table 13). Internal 2 Drive decoding specifies support for a maximum of two floppy drives.
External 2-to-4 Drive decoding expands support for four floppy drives but requires an external 2-to-4 decoder. The
drive select encoding is determined by the EXTx4 bit in CR05.
The FDC37N769 can also internally swap drive 0 and drive 1 using the Swap Drv 0, 1 bit in CR05. Table 12
illustrates Internal 2-Drive decoding with drive 0 and drive 1 swapped. Table 14 illustrates External 2-to-4 Drive
decoding with drive 0 and drive 1 swapped.
Table 11 - Internal 2 Drive Decode: Drives 0 and 1 Not Swapped
DRIVE SELECT OUTPUTS
(ACTIVE LOW)
MOTOR ON OUTPUTS
(ACTIVE LOW)
DIGITAL OUTPUT REGISTER
Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0
nDS1
nDS0
nMTR1
nBIT 5
nBIT 5
nBIT 5
nBIT 5
nBIT 5
nMTR0
X
X
X
1
X
X
1
X
1
X
X
0
1
X
X
X
0
0
0
1
1
X
0
1
0
1
X
1
0
1
1
1
0
1
1
1
1
nBIT 4
nBIT 4
nBIT 4
nBIT 4
nBIT 4
X
0
0
SMSC DS – FDC37N769
Page 21 of 137
Rev. 12/21/2000